NEXT GENERATION SUBTRACTOR DESIGN USING GDI TECHNOLOGY

Authors

  • Divyasre T UG Scholar, Department of Electronics and Communication Engineering, KIT-Kalaignar Karunanidhi Institute of Technology, Coimbatore, Tamil Nadu, India. Author
  • Karumanchi Karishma UG Scholar, Department of Electronics and Communication Engineering, KIT-Kalaignar Karunanidhi Institute of Technology, Coimbatore, Tamil Nadu, India. Author
  • Aishwarya S UG Scholar, Department of Electronics and Communication Engineering, KIT-Kalaignar Karunanidhi Institute of Technology, Coimbatore, Tamil Nadu, India. Author
  • Yogeshwaran K Assistant Professor, Department of Electronics and Communication Engineering, KIT-Kalaignar Karunanidhi Institute of Technology, Coimbatore, Tamil Nadu, India. Author

Keywords:

GDI Technique, Low Power, Semiconductor Device Count, Area Reduction

Abstract

Full subtractor is design of an energy-efficient, high-speed, and low-power full subtractor using the Gate Diffusion Input (GDI) technique. Full subtractors are essential in digital circuits for arithmetic operations, but traditional designs may not meet modern requirements. The GDI technique offers a promising solution by reducing transistor count and improving energy efficiency. It represents the significance of full subtractors, introduces the GDI technique, outlines the proposed design methodology, and discusses simulation results. The aim is to demonstrate a practical approach for achieving efficient full subtractors vital for various digital systems.

References

Sandip B. Rahane, Tushar T. Korade, Gate Diffusion Input Full Subtractor Circuit using 130nm Technology, IJSRD - International Journal for Scientific Research & Development, Vol. 5, Issue 04, 2017, ISSN (online): 2321-061.

Swathi Kiran, M. Amarnath Reddy, Performance Analysis and Implementation of High Speed Full-Adder Using Modified GDI Technique, International Journal for Advanced Research in Science and Technology (IJARST), Volume 11, Issue 04, Apr 2021, 20=24, ISSN 2581-4575.

Swetha S, Reddy NSS and Hemalatha R, Optimize Design of full subtractor using 45nm Technology, Int. Res. J. of Science & Engineering, 2017; Vol. 5 (5): 71-75, ISSN: 2322-0015.

Krishnendu Dhar, Aanan Chatterjee, Sayan Chatterjee, Design of an Energy Efficient, High Speed, Low Power Full Subtractor Using GDI Technique, Proceeding of the 2014 IEEE Students' Technology Symposium, 978-1-4799-2608-4/14/$31.00 ©2014 IEEE, pp. 109-204

S Suma, Kiran V, Design and Analysis of a Full Subtractor using Various Design Techniques, International Research Journal of Engineering and Technology (IRJET), Volume: 09 Issue: 10, Oct 2022, e-ISSN: 2395-0056, p-ISSN: 2395-0072, Impact Factor value: 7.529, ISO 9001: 2008 Certified Journal, pp. 909-913.

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Published

2024-04-26

Issue

Vol. 15 No. 1 (2024): INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING AND TECHNOLOGY (IJECET)

Section

Articles

License

Copyright (c) 2024 Divyasre T, Karumanchi Karishma, Aishwarya S, Yogeshwaran K (Author)

Creative Commons License

This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.

How to Cite

NEXT GENERATION SUBTRACTOR DESIGN USING GDI TECHNOLOGY. (2024). INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING AND TECHNOLOGY (IJECET), 15(1), 7-18. https://iaeme-library.com/index.php/IJECET/article/view/IJECET_15_01_002